The invention relates generally to hardware simulation and more specifically to the automation of hardware simulation using symbolic models.
System development for complex electronic and computer systems requires the integration of work performed by researchers, engineers and software developers. A researcher""s work serves as an input for development engineers, who are responsible for implementing a practical application of the researcher""s solution or improvement. Early in the system development process, integrated circuit (IC) developers translate the statement of the proposed solution and implement the required functionality on application specific integrated circuits (ASICs). Thereafter, the ASICs are integrated on printed circuit boards, also known as circuit packs, based upon the functions they perform in the overall system architecture. Systems may comprise hundreds of ASICs and dozens of circuit packs. Developers group circuit packs in racks, and racks are grouped in bays. Depending upon the functions required and upon the system complexity, the system may include multiple bays.
It is a disadvantage in system engineering that ASIC and board development usurp a large part of the development cycle, leaving very little time for the other development tasks. For instance, software development cannot commence until hardware development is almost complete, because the hardware functionality serves as an input to the software design. Similarly, test engineers cannot begin hardware or software testing, or even devise test cases, until the hardware and software is nearly finished. For this reason, testing is often left to the end of the development cycle, and is performed under great time pressure. Furthermore, developers are not the only persons impacted by the ASIC development process; persons charged with marketing a system, or with preparing system documentation cannot commence their tasks until the hardware development is nearly complete.
To aid the development process, engineers use various tools for simulating hardware behavior. For instance, at the integrated circuit (IC) level, computer-aided tools like SYNOPSIS(trademark) and PCAD(trademark) are used to simulate various behavior useful to the integrated circuit developer. Very High Speed Integrated Circuit Hardware Development Language (VHDL), IEEE standard 1076 (1987), and VERILOG(trademark) are other known tools used by IC developers for simulating behavior expected from an ASIC. Similarly, on the board level, developers use tools such as ORCAD(trademark) to simulate board layout and other behavior useful to the board developer. There are also known tools useful to the software engineer for simulating behavior of interest. Some of these tools are MATLAB(trademark) and MATHCAD(trademark).
Symbolic modeling is the use of symbols to represent lower level components of a system. One form of symbolic modeling is functional modeling, which uses symbols to represent functionality of system components, as described in, for example, International Telecommunications Union (ITU)/ETSI Standards ITU-T G.805 and ETSI ETS 300 417-1-1. There is no tool, however, which simulates behavior at the bay, rack or system level. Furthermore, no automatic generator of symbolic models exists. As a result, the time to develop, integrate and test a system (hardware and software) remains a function of the time taken to develop ICs and boards to a sufficient extent that test engineers and software developers may begin their tasks. There is a need, therefore, to develop a means for automatically generating a hardware simulator which may use symbolic modeling and which will allow other critical development tasks, such as software development, training of test engineers and training of marketing engineers, to commence earlier in the development cycle. There is also the need to develop such an automated hardware simulation generator which allows for the concurrent development of symbolic models and aids in refining and correcting researcher and IC developers"" documents; this in turn, could allow software, test and marketing engineers to save hundreds of man-hours by eliminating their need to question researchers and IC developers on a one-to-one basis.
The present invention is an apparatus for automatically generating symbolic models and for automatic development of an associated system level hardware simulator. The apparatus comprises an interface and a graphics display for selecting and displaying symbolic model symbols, preferably as per ITU or ETSI standards. For each displayed symbol, the user may specify the symbol""s functionality. The symbol is made specific to a hardware mapping by inputting, via an editor, a memory register location, a memory bit location name, a memory bit name, a memory register type, a memory size, the reset or initial state of the register content, and a register mode. The user also selects, via the editor, a direction for each symbol (sink, source or sink and source), a layer priority for each symbol, and chooses the bit sense condition for the associated register as active high or active low. In addition to standard predefined symbolic model symbols, the apparatus includes the ability for a user to define, store and later recall for use, a symbolic model symbol and the symbol""s specified functional characteristics.
To use the simulator, the system of interest is iteratively divided into its constituent bays, the bays are divided into racks, the racks are divided into circuit packs, and the circuit packs are divided into integrated circuits (ICs). After each divisional iteration, a system layer name is defined for the resulting subset of components and a symbolic model symbol is chosen for the subset. The symbolic model symbol specifications are then input via the editor. Thus, each symbolic model symbol captures the functionality of the bay, rack, circuit pack and ICs in its functional hierarchy. The system is divided, the system layer named, symbols chosen, and functionality specified, until the entire system of interest is described.
From the symbol specifications and system layer associations, the simulator constructs and graphically displays an image of a symbolic model. Within the simulator, each symbolic model symbol has a simple input/output memory allocated to it. The symbolic model symbol reads inputs from previous connections determined by the layer and layer priority of the symbolic model symbol, that is from its source symbolic model symbol, and updates its register contents as per its specification. Each symbol then broadcasts its updates to symbolic model symbols whose input depends on the current state of the symbolic model symbol output, again according to the layer and layer priority of the symbolic model symbol. The model interconnections are shown graphically on the display. The user may interact with a displayed symbolic model and can modify the model by altering the interconnections of the displayed symbolic model, which alteration will result in corresponding modification of the connections of other interconnected symbolic model symbols and their associated input/output memories. One cycle of simulation is completed when a complete chain of registers is updated from input to output in both sink and source directions. In this mode, the simulator is a state machine and the user may access a memory map for each symbol.
In another mode, the simulator may be operated as a real time simulator. Each symbolic model symbol is linked to IC simulation language files such as Very High Speed Integrated Circuit Hardware Description Language (VHDL) or VERILOG(trademark) files used by the application specific integrated circuit developers. These files contain timing information specifying the real-time propagation through the IC""s represented by the symbol. Further real-time information may be input to capture the time delays imparted by the connections between symbolic model symbols. By linking to IC simulation language timing information and inputting other delay information associated with the symbolic model, the simulator becomes a real-time event simulator.